In integrated circuit design, great emphasis is placed on the operating speed of the circuit. For transistor-transistor logic (TTL) gates with totem-pole outputs, this implies a high operating current. However, during testing procedures, the output of a circuit may be shorted to ground. If the short circuited output current (IOS) is too large for too long, parts of the integrated circuit device will be damaged.
In its simplest form, a TTL gate with a totem-pole output comprises an input transistor (also known as a phase splitter), two output transistors (referred to here as upper and lower output transistors), and a current limiting resistor. The base of the phase splitter is coupled to the TTL gate input, its emitter is coupled to the base of the lower output transistor and its collector is coupled to the base of the upper output transistor. The collector of the lower output transistor and the emitter of the upper output transistor are coupled together and form the output of the gate. The emitter of the lower output transistor is coupled to ground and the collector of the upper output transistor is coupled to a voltage source through the resistor. In addition, the load to which the gate output is coupled has a certain capacitance.
In operation, the phase splitter acts as a common collector to the upper output transistor, turning it on when the input is low, and acts as an emitter follower to the lower output transistor, turning it on when the input is high. The capacitance at the gate output must be charged and discharged for gate switching to take place. The upper output transistor acts as a current source to charge the capacitance while the lower output transistor acts as a current sink to discharge the capacitance. If the capacitance can be made to charge more rapidly, the overall speed of the gate can be increased.
One method used in the prior art to more rapidly charge the capacitance has been to lower the value of the resistor coupled to the collector of the upper output transistor. This permits a higher current to flow through the upper output transistor into the output. A crucial disadvantage of this method is that the output current may be excessive in the event that the output is shorted to ground; the upper output transistor can be destroyed as a result, since shorting the output to ground is a common test given after a circuit has been constructed.
Therefore, a need has arisen to provide a circuit for providing a fast output low-to-high transition while maintaining the short circuited output current at a safe level.